1. Field of the Invention
The present invention relates to the design of integrated circuits and, more particularly, to the layout of the objects, i.e., devices, pads, and networks, of the integrated circuit.
2. Description of Related Art
Heretofore, physical synthesis of an Integrated Circuit (IC) involved two distinct successive phases of placement and routing, each of which is typically performed by separate, specialized software packages, called a placer and a router, designed to perform the corresponding function. The placer arranges the circuit components (devices and pads) on a layout surface while the router defines paths connecting placed components on the layout surface, on which conductors that carry electrical signals are run. Since the placer typically takes limited routing information into consideration during its operation, it exercises restricted control on routing topology.
The performance of Radio Frequency Integrated Circuits (RFICs) is highly sensitive to interconnect parasitic effects, which are artifacts of the physical layout of the circuit. Interconnect parasitics are a function of the routing topology, and can vary with differing topologies.
A typical circuit synthesis design flow for RFICs, based on automatic sizing with layout parasitics, explores the design space, iteratively examining different sizes of various devices until a combination thereof is found that meets or exceeds the circuit specifications. Corresponding to each set of device sizes that is visited by the circuit synthesis tool, a placed and routed layout is realized from which interconnect parasitics are estimated in turn.
In the prior art, as the device sizes change during the circuit synthesis process, the placements obtained therefrom often make the router create different routing topologies, due to insufficient routing information modeled during the placement phase. This has the effect of making the layout parasitics change significantly from one layout to another, which in turn interferes with the synthesis tool's search for the optimal device sizes for a design.
Additionally, in the prior art, due to the lack of tangible representation of the structure of an interconnect during placement and routing, it was inconvenient to specify keep-out areas for interconnects, to prevent coupling effects among sensitive interconnects and components in the design.
It would, therefore, be desirable to overcome the above problems by providing a method whereupon interconnects are treated as regular placeable objects; and the placement of devices, pads and interconnects of an integrated circuit is accomplished simultaneously. By performing simultaneous placement and routing, the routing topology of critical interconnects, intended by the designer, is captured as an integral input (example-based routing) and enforced as an essential constraint within the placement process. Therefore, this eliminates the unpredictability of varying routing patterns obtained by running the router on a placed layout as a subsequent step during the circuit synthesis process. Further, the simple representation of an interconnect in terms of individual connected segments permits convenient specification of keep-out areas around sensitive interconnects allowing coupling-aware placement. In addition, the simple interconnect representation in the placer encourages the use of accurate simulation models in the synthesis flow, increasing the accuracy of the results. Additional features and advantages of the present invention will become apparent to those of ordinary skill in the art upon reading and understanding the following detailed description.